UltraRAM - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
Release Date
2020.2 English

The UltraRAM sheet covers power estimates of the dedicated 288 Kb UltraRAM block. The UltraRAM in Versal has more flexibility than UltraScale+. The Add Memory IP wizard does not yet support UltraRAM. So, the resources must be estimated or calculated manually. The settings that define UltraRAM structure include the following:

Cascade Group Size
UltraRAM blocks support cascading to create larger memory arrays while reducing the overall power by enabling only one UltraRAM of a cascade at a time. Example: 20 UltraRAM blocks with a Cascade Group Size of 4 represents 20/4 = 5 sets of cascaded UltraRAM of 4 blocks each. If there is no cascading, use 1 as the value of cascade group size. The Cascade Group Size applies to vertical cascading, increasing array depth.
The optional UltraRAM pipeline registers are IREG_PRE (input) or REG_CAS (cascade). The default value is Cascade Group Size divided by 3. If there is no UltraRAM cascading, only IREG_PRE can be used which corresponds to a Latency of 1.
Chooses between URAM288 (no ECC) and URAM288_with_ECC.

The following settings define the UltraRAM activity:

Sleep Rate
The percentage of time the UltraRAM SLEEP input pin is asserted. The value of Auto is also supported for Automatic Sleep Mode.
Average Inactive Cycles
The average number of consecutive inactive cycles when in Sleep Mode. The minimum value is > 10 or the Cascade Group Size minus 2.
Input Toggle Rate
The average toggle rate of the data inputs (DIN) for both ports A and B.
Output Toggle Rate
The average toggle rate of the data outputs (DOUT) for both ports A and B.
Clock (MHz)
Clock frequency of the UltraRAM or UltraRAM module.

Following are the values specified for the UltraRAM ports A and B:

Data Width
Specify the exact data width if less than the maximum 72 bits.
Enable Rate
The percentage of time the UltraRAM is enabled.
Write Enable
The percentage of time the write enable input is asserted, independently of the Enable Rate. The write enable pins are the UltraRAM RDB_WR_A and RDB_WR_B pins.
Note: When you specify Enable Rate and Sleep Rate, for each of the ports A and B, the sum of (Enable Rate / Cascade Group Size) and Sleep Rate must not exceed 100%.