Using the Memory Generator Wizard for Distributed Memory - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
UG1275
Release Date
2020-12-04
Version
2020.2 English

The Memory Generator wizard allows you to enter distributed memory information in the Logic sheet. You can access the Memory Generator Wizard by clicking the Add/Manage IP button on the Summary sheet or the Manage IP button on the IP Manager sheet, or the Add Memory button on the Logic sheet. The XPE Memory Generator wizard provides a simplified method of populating the Logic sheet with rows related to distributed memory. To understand the capabilities of distributed memory and the settings, you enter within XPE, see the Versal™ ACAP Configurable Logic Block User Guide.

In the Distributed Memory tab of the XPE Memory Generator dialog box, fill out the information in the dialog box for one distributed memory Memory Type in your design. The following fields exist in the Distributed Memory tab:

Memory Type
Select the type of memory your design will use.
  • Single-Port RAM
  • Simple-Dual Port RAM
  • Single-Port ROM
  • Dual-Port ROM
Note: For a description of these memory types, see the Versal ACAP Configurable Logic Block User Guide.
Clock
Represents the clock frequency at which the distributed memory operates. For dual-port memory types, XPE assumes the same clock frequency for both ports.
Note: You should create clocks as a pre-step using clocking wizard and select the clock from drop-down list. Create a clock before using clocking wizard and select the clock from the drop-down list.
Toggle
Represents the average toggle rate of the data signals. A toggle rate of 25% means that the data signals toggle each every fourth clock cycle.
Width
Represents the bit width for each word in the memory.
Depth
Represents the depth of the memory. Width × Depth is the total number of bits in the memory.
Registered Inputs
Used to represent whether the memory inputs will be registered (Registered Inputs selected) or not (Registered Inputs deselected). For a description of input registering, see the Versal Configurable Logic Block User Guide.
Registered Outputs
Represents whether the memory outputs are registered (Registered Outputs selected) or not (Registered Outputs deselected).
Module name
Allows you to assign a name to the generated distributed memory configuration. This will help distinguish multiple configurations in the XPE sheets.

Once the configuration fields are filled out and created, a new row in the Logic sheet is filled in with the information you have entered in the dialog box.