Using the Processing System Sheet - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
UG1275
Release Date
2020-12-04
Version
2020.2 English

Versal™ ACAP integrates a feature-rich 64-bit dual-core Arm® Cortex™ -A72 and dual-core Arm Cortex™-R5F based processing system (PS), Xilinx programmable logic (PL) architecture, and AI Engine in a single device.

Low Power and Full Power Domains

The PS (Processor Subsystem) sheet is divided into two domains: Low Power Domain and Full Power Domain. These power domains can be turned on and off. The following figures show the Low Power and Full Power domains.
Figure 1. Low Power Domain
Figure 2. Full Power Domain

Processor and PLLs

The PS for Versal architecture integrates a feature-rich 64-bit dual-core Arm® Cortex™ -A72 (APU) for full power and dual-core Arm® Cortex-R5F (RPU) based processing system (PS) for low power domains. APU PLL is available in the full power domain and generates clocks for Arm Cortex-A72 core, L2 Cache, FPD Interconnect, and CCI. RPU PLL is available in the low power domain and generates clocks for Arm Cortex-R5F core, TCM, OCM, and LPD Interconnect.

Note: L2 cache must be enabled when using A72s, XPE does this automatically and adds power to FPD.

Memory and I/O Interfaces

The Arm® Cortex-A72 and Cortex-R5F CPU systems also include on-chip TCM, OCM memory, L2 Cache, and a rich set of peripheral connectivity interfaces.

CCI (Cache Coherent Interconnect)

The CCI refers to the block which combines part of interconnect and coherency functions into a single block. The Load field value can range from 0% -100% depending upon the application. The value for Load is the same as the Load for Interconnect. The maximum permissible frequency is the same as the range of APU frequency for a corresponding speed grade.

LPD I/O Interfaces

The three different low power domain I/O interfaces that are supported are listed here:

Dual GEM
Versal device PS has 2 GEMs (Gigabit Ethernet MAC) shared between PS and PMC. The field GPIOBs represents the number of pairs of I/Os used. Each GEM needs six pairs of I/Os (12 I/Os) with a maximum clock frequency of 125 MHz. Hence, there is an option of six or twelve (pairs) for using single or both the GEMS respectively. The usage rate should be entered with expected switching rate of the interface.
USB
PS and PMC has shared USB2 support. The number of I/Os required for USB data transfer is six pairs. Hence it has the option of 0 and 6. The usage rate should be entered with expected switching rate of the interface. The maximum operating frequency is 250 MHz.
Std Perf IOs
The number of I/Os being used should be entered in pairs. The maximum frequency permitted is 450 MHz. The usage rate should be entered with expected switching rate of the interface.
Note: The maximum number of I/Os per Bank is 26 (13 pairs). Each GEM interface requires 6 pairs or 12 I/O's and these I/Os are located in PMC Bank1.