Using the Soft Memory Interface Configuration Wizard - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
Release Date
2020.2 English

The Memory Interface Configuration wizard allows you to create the IPs for the I/Os involved in the interface between a Xilinx® device and external memory. It provides a simplified method of filling in the memory interface I/Os in the XPE spreadsheet. When you configure a memory interface using the wizard, rows are added to the IP Manager sheet, and to the I/O sheet for each output line (for example, Data, Address, and Clock) from the Xilinx device that is applied to the external memory. The wizard also places rows on the Clock sheet, and on the Logic sheet. Resources are added representing typical usage to implement the physical controller and user interface layer.

Important: The Memory Interface Configuration wizard does not support all memory interface standards or all interface parameters for the supported standards. The wizard covers many of the common Memory Interface Standards. For a specific standard there could be more pins associated than configured by the wizard. In these cases you might need to modify the output of the wizard or enter the extra pins manually in the I/O sheet for your specific case. Also, if a selection is not available for a specific field, you might be able to manually override the selections in the field. For Better accuracy, create IP in Vivado® and generate resource information to manually enter in to XPE.

The following fields are available in the XPE Memory Interface Configuration dialog box:

The Memory Interface Configuration wizard supports the following I/O Memory Controller Standards:
Soft Memory Controllers
  • DDR3, DDR3L, and LPDDR3
  • DDR4
  • QDRII+ and QDRIV
Note: You can also manually enter a memory interface of any other standard in the XPE spreadsheet.
Bank Type
The appropriate bank type, where the choice exists between XP or HD I/O bank.
Mem Config
The appropriate memory configuration.
Input Termination (DQ/S)
Refers to the DQ (data) and DQS (data strobe) pins. For memory interfaces using the HD or XP banks, select RTT_40, RTT_48, RTT_60 or external termination (no entry).
Data Rate
The target data rate for your memory device.
Address Width
The total number of address lines used in the interface, which includes Row, Column, Bank, and, if used, Rank and CS lines.
Data Width
Select appropriate Data width for the selected memory interface.
Read/Write (%)
The percentage of the time the memory interface is used for reading from and writing to the external memory. The total must be less than or equal to 100% and the interface is assumed to be idle for 100% - (Read% + Write%) of the time. This is reflected in the Output Enable, Term Disable and IBUF Disable percentages.
Number of Interfaces
The number of memory interfaces that will use the settings that you are currently entering in the dialog box. When the I/O sheet is populated with the outputs to external memory, the number of pins for each type of line (for example, Address, Data, and Clock lines) will reflect the number of Interfaces you specify.
Add typical link layer logic
This option allows you to automatically generate the resources of the link layer logic for a specific memory interface. This is not applicable for Hard Memory Controllers.
Module Name
Allows you to assign a name to the generated configuration. This helps distinguish multiple configurations on the I/O sheet.

Once configured and created, new rows in the I/O sheet are populated with the information you entered in the dialog box.