Versal ACAP Auxiliary Power Domains - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
UG1275
Release Date
2020-12-04
Version
2020.2 English

The Versal™ devices include two major auxiliary power rails. The auxiliary power rails that are typically associated with the Analog IPs, I/O, or Battery-powered domain, are listed in the following table:

Table 1. Auxiliary Power Domain Descriptions
Auxiliary Power Domain Description
PMC/PS Aux Rail (VCCAUX_PMC) This is the Auxiliary supply that is used by the circuitry in the PMC and PS PLLs, I/O, and SysMon. This supply is also used to run the Battery-Powered domain when the device is up. When the device is off, the Battery-Powered circuitry is switched to VCC_BATT. VCCAUX_PMC should be up for the Versal device to boot.
PL Aux Rail (VCCAUX) This Aux supply is used by the PLLs, IO, and Satellite SysMons outside the PS. The core supplies associated with the modules that use this Aux supply can be VCCINT, VCC_SOC, VCC_IO, and VCC_RAM.

Multiple power supplies are required to power a Versal device. The following table describes the logic resources typically available in these devices and their corresponding power supply:

Table 2. Versal ACAP Resources and Corresponding Power Supply
Power Domain Power Supply Resources Powered
PMC Domain

VCC_PMC

VCCO_500

VCCO_501

VCCO_503

VCCAUX_PMC

VCCAUX_SMON

VCC_FUSE

  • This is an Always On domain. PMC is required always to be powered for Versal ACAP to be configured and functional during run-time.
  • Platform management controller
  • PMC IO bank, including flash, I2C, QSPI, and other interfaces
  • PMC and PS PLL
  • SYSMON
  • eFuse Programming
PS Domain

VCC_PSLP

VCCO_502

PS Low Power domain including
  • Real time processing unit (RPU)
  • TCM
  • OCM
  • IO interface for GEM, USB, and Std performance IOs
VCC_PSFP PS Full Power Domain
  • Application processing unit (APU)
  • L2 Cache
  • CCIX
System Domain VCC_SOC
  • Network on Chip
  • Hardened DDR memory controller
  • Interconnect (HSR crossing)
VCCAUX
  • Clock managers (MMCM, PLL, and DCM)
  • IODELAY/IDELAYCTRL
  • All output buffers
  • Differential input buffers
  • VREF-based, single-ended I/O standards, for example, HSTL18_I
VCC_IO
  • IBUF
  • OBUF
  • ISERDESE
  • IDDR
  • IFF
  • OSERDESE
  • ODDR
  • OFF
  • IDELAYE
  • ODELAYE
  • RX_BITSLICE
  • TX_BITSLICE
  • TX_BITSLICE_TRI
  • RXTX_BITSLICE
  • BITSLICE_CONTROL
  • IDELAYCTRL
  • XPLL Controller
PL Domain VCCINT All CLB resources
  • All routing resources
  • Entire clock tree, including all clock buffers
  • Block RAM
  • DSP slices
  • All input buffers
  • AI Engines
  • Logic elements in the IOB (ILOGIC/OLOGIC)
  • Clock Managers (MMCM, DPLL, and DCM)
  • Hard Blocks like PCIe, MRMAC, DCMAC, and CPM
VCC_RAM
  • Memory array of block RAMs
  • Clock network power
  • DPLL
VCC_CPM5 CPM5
Note: It is available only for some premium series devices.
VCCO
  • All output buffers
  • Some input buffers
  • Input termination
  • Reference resistors to DCI

MGTAVCC

MGTAVTT

MGTVCCAUX

  • Analog supply voltages for PMA circuits of transceivers
  • Transceiver termination circuits
  • Quad PLL
Battery Domain VCC_BAT Battery domain powers RTC core and battery backed RAM

The following table shows the dependency between the mentioned power domains by providing the list of domains that have to be functionally available if a target domain is expected to be functional. A domain is functionally available if it is powered and its reset is released. The powered domains can operate at the voltage levels that are supported by that rail.

Table 3. Dependency of Power Domains
Target Domain Other Core Domains that have to be up Required Supplies
PMC None VCC_PMC, VCCAUX_PMC, and VCC_50x
PS-LPD PMC VCC_PMC, VCCAUX_PMC, VCC_50x, and VCC_PSLP
PS-FPD PMC, PS-LPD VCC_PMC, VCCAUX_PMC, VCC_50x, VCC_PSLP, and VCC_PSFP
NoC with DDR PMC, VCC_AUX VCC_PMC, VCCAUX_PMC, VCC_50x, VCC_SOC, and VCC_AUX
PL PMC, NoC VCC_PMC, VCCAUX_PMC, VCC_50x, VCC_SOC, VCCINT, VCCAUX, and VCC_RAM