XPE Power Modes - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
UG1275
Release Date
2020-12-04
Version
2020.2 English

Versal™ devices support different power modes of operation in XPE. The predefined independent power modes can be categorized into PS (Processing System) and PL (Programming Logic) power modes. You can select a power mode based on the power saving requirements of your application. The power modes are described in this section.

PS Power Modes

The PS power modes are described as follows.
Full Power Domain (FPD)
Primarily comprises of Dual A72 cores, L2 Cache, FPD Interconnect, and CCI.
Low Power Domain (LPD)
Primarily comprises of Dual R5 cores, TCM, OCM, LPD Interconnect I/Os.
Figure 1. PS Power Modes
The predefined PS power modes are described in the following table.
Table 1. PS Power Modes
PS Power Modes Description Recommended Use
User Mode This mode has no predefined configuration. You can configure the complete PS Module based on your design requirements. This mode is used to define the expected full processing mode of the processing subsystem. Also, it is used to estimate the worst case power for the processing subsystem.
Linux Boot Idle
  • FPD powered on, APU's idle
  • LPD powered. RPU's idle that is load @0%
This mode emulates the linux boot time and the corresponding configuration can be used to determine power while booting.
R5s_Idle_FPD_Off
  • FPD is powered off
  • LPD is powered on and RPU is idle where the load is 0%
This mode is suggested for PL based designs which may need LPD rarely and APU is never used. This results in total power saving of FPD and dynamic power saving of LPD during operation.
Deep Sleep
  • Both LPD and FPD are powered down, both static and dynamic Power is 0
  • PMC is idle at 20 MHz
This mode is suggested for power saving when the design is mainly PL based.
Deep Sleep - Fast Resume
  • FPD is powered off, FPD staticPower is 0
  • LPD is powered on but RPU is off/clock gated
  • PMC is idle at 20 MHz
 
R5s_Idle_1_A72_Active
  • RPU is idle
  • One of the APU cores is idle
  • The second APU core is operational with a load of 80%
Used to save power of the RPU core and 1APU core
R5s_Idle_1_A72_250MHz
  • LPD is on with RPU idle where the load is 0%
  • FPD is shutdown. The static power of FPD is 0
This configuration is useful if none of the blocks in the FPD are used in the design, hence fully shutting down the FPD saves static power. It is mainly used for real-time applications only
R5s_Idle_FPD_Off_DDR_Self_Refresh
  • FPD is powered off
  • LPD is powered on and RPU is idle where the load is 0%
  • DDR is in self refresh mode
 
Note: PMC is never completely powered off in any of the above modes.

PL Power Modes

User Mode
You can define this mode similar to PS User Mode. All the PL voltage rails are operational. You can manually change any setting in this mode.
Clock Gated Mode
In this mode, the PL clocks are gated the same way as a zero frequency clock for Logic, BRAM, URAM and DSP. Hence dynamic power of these blocks is zero but static power is present. This mode does not affect NOC-DDRMC, AI Engine, and GT which remain fully operational. This mode is suggested for power saving when the design mainly depends on AI Engine, GT, and NOC-DDRMC.
Powered Off Mode
All the PL power rails including AI Engine, NOC DDRMC, and GT are zero. Hence, no PL static power is reported in this mode. This mode is a suggested power saving mode when the design is mainly PS based.