DDRMC - 2020.2 English

Versal Architecture AI Core Series Libraries Guide (UG1353)

Document ID
UG1353
Release Date
2020-12-04
Version
2020.2 English

Primitive: DDR4 memory controller

  • PRIMITIVE_GROUP: ADVANCED
  • PRIMITIVE_SUBGROUP: BUFFER

Introduction

The DDRMC is the DDR4 memory controller block in Versal devices. This element is not intended to be instantiated, used, or modified outside of Xilinx-generated IP.

Design Entry Method

Instantiation No
Inference No
IP and IP Integrator Catalog No

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