Creating a Block Design with IP Integrator - 2020.2 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2021-03-26
Version
2020.2 English

Following are the typical steps to create a Versal™ ACAP design in the Vivado IP integrator:

  1. Create a new Vivado Design Suite project.
  2. Create a block design in the IP integrator, and instantiate a Control, Interfaces and Processing System (CIPS) processor, along with any other Xilinx® IP or your custom IP, such as a packaged RTL block.
    Important: The Vivado tools require the CIPS IP to be present in the design to create the programmable device image (PDI). All Versal ACAP designs require the CIPS IP, which contains the PMC block required for device configuration and monitoring. For more information, see the Control, Interface and Processing System LogiCORE IP Product Guide (PG352).
  3. Run block automation and connection automation, which helps complete your design by adding other IP, such as NoC and memory controllers.
  4. Complete interface connectivity of the blocks that were not automatically connected.
  5. Use the Address Editor to define the address map.
  6. Validate the block design to make sure that the design is correct by construction.
  7. Generate output products for the IP in the block design with the correct synthesis mode options.
  8. Generate the top-level wrapper, which instantiates the block design.
  9. Run the top-level design through synthesis and implementation.
  10. Ensure all design requirements are met.
  11. Export the platform definition to the Vitis software development platform.
  12. Create your software application in the Vitis software platform and generate an ELF file.
  13. Run or debug your application on the target hardware.