The Versal™ ACAP tool flow introduces a pair of IP cores, the axi_noc and the axis_noc. These IP cores act as logical representations of the Versal ACAP programmable network on chip (NoC). The axi_noc supports the memory mapped AXI protocol while the axis_noc supports the AXI4-Stream protocol. A Versal ACAP platform design might include multiple instances of each of these IP cores. Each instance specifies one or more connections to be mapped onto the physical NoC, along with the QoS requirements for each connection.
The Vivado IP integrator automatically aggregates the connectivity and QoS information from all of the logical NoC instances to form a unified traffic specification. This traffic specification is used to compute an optimal configuration for the NoC. You can use the IP integrator to customize and generate NoC IP cores. The IP configuration allows you to set the number and type of input and output ports, define the connectivity through the NoC, and specify the memory controller configuration.
The DDR4 memory controllers (DDRMCs) are integrated into the axi_noc IP. The IP customization in the IP integrator also allows connecting memory controllers to the NoC and configuring the controllers and external DDR memory parameters. An instance of the axi_noc can be configured to include one, two, or four instances of the integrated DDRMCs. If two or four instances of the DDRMCs are selected, the DDRMCs are configured to form a single interleaved memory to all masters connected through the NoC.
report_power in the Vivado Design Suite or using the Xilinx Power Estimator (XPE). To use the XPE, import the NOC_Power.xpe file from the NoC design into XPE to get a more accurate estimation of the
NoC and total system power.