Creating a Design with SmartConnect IP - 2020.2 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2021-03-26
Version
2020.2 English

The SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. The SmartConnect core is tightly integrated with the Vivado tools to automatically configure and adapt to connected AXI master and slave IP with minimal user intervention. The SmartConnect IP can be optimized for maximum performance or for low area, depending on the connected interfaces.

For more information, see the SmartConnect LogiCORE IP Product Guide (PG247).