You can use RTL to create your Versal™ ACAP design. However, to take advantage of all of the features in the Versal ACAP, Xilinx recommends using the Vivado® IP integrator.
Xilinx recommends using the Vivado IP integrator to instantiate and configure the CIPS and NoC IP. However, you do not need to use the IP integrator for your entire design. You can configure the CIPS and NoC in IP integrator, specify the interface to the rest of the design, and instantiate the resulting block design in the top-level RTL. Using this approach, IP integrator automates the CIPS and NoC configuration, allowing you apply additional changes as needed.