Running Synthesis - 2020.2 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2021-03-26
Version
2020.2 English

Synthesis takes in RTL and timing constraints and generates an optimized netlist that is functionally equivalent to the RTL. In general, the synthesis tool can take any legal RTL and create the logic for it. Synthesis requires realistic timing constraints.

For additional information about synthesis, refer to the following resources:

Note: For more information on timing constraints, see this link in the Versal ACAP System Integration and Validation Methodology Guide (UG1388).