Confirm if the PS/PMC PLLs are stable and locked, clocks are in active state, and their divisor, multiplier, and source are correctly configured.
- Check the clocks configured correctly to each module with respect to speed grade.
- Read the CRx(CRL, CRF and CRP) modules registers for checking clocking.
To read the QSPI Clock Register using XSCT, run the following command:
xsct%mrd -force 0xF1260118
Register Name | Address | Width | Type | Reset Value | Description |
---|---|---|---|---|---|
QSPI_REF_CTRL | 0xF1260118 | 32 | rw | 0x01000400 | This register controls this reference clock |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:25 | rw | 0x0 | reserved |
ClkAct | 24 | rw | 0x1 | Clock active signal. 0 = disable the clock. 1 = enable the clock. |
Reserved | 23:18 | rw | 0x0 | reserved |
Divisor | 17:8 | rw | 0x4 | 10-bit divider value: 0: divide by 1 1: divide by 1 2: divide by 2 etc 1023: divide by 1023 Note: reset value is divide by 4. (aka DIVISOR0) |
Reserved | 7:3 | rw | 0x0 | reserved |
SrcSel | 2:0 | rw | 0x0 |
000: PPLL 011: NPLL Others: reserved |