Using VIO Cores - 2020.2 English

Versal ACAP System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2021-02-04
Version
2020.2 English

The Virtual Input/Output (AXIS-VIO) core allows you to monitor and drive internal device signals in real time. Use this core when it is necessary to drive or monitor low speed signals, such as resets or status signals. The AXIS-VIO debug core must be instantiated in the design and can be used in both IP integrator and RTL. The AXIS-VIO core is available in the IP catalog for RTL-based designs and in IP integrator.

For information on taking measurements with an AXIS-VIO core, see Setting Up the AXIS-VIO Core to Take a Measurement in the Vivado Design Suite User Guide: Programming and Debugging (UG908).