The following table outlines the required register map such that a kernel can
be used within the Vitis tools and XRT. The control register
is required by kernels that specify
ap_ctrl_chain execution models, while the interrupt related registers are only
required for designs with interrupts. All user-defined registers must begin at location
0x10; locations below this are reserved.
If your RTL design has a different execution model, it must be adapted to ensure that it will operate in this manner.
ap_ctrl_nonedo not require the control registers described below.
|0x0||Control||Controls and provides kernel status.|
|0x4||Global Interrupt Enable||Used to enable interrupt to the host.|
|0x8||IP Interrupt Enable||Used to control which IP generated signal are used to generate an interrupt.|
|0xC||IP Interrupt Status||Provides interrupt status.|
|0x10||Kernel arguments||This would include scalars and global memory arguments for instance.|
The following table shows the control signals that are accessed through the
control register (
offset 0x0). The available signals are used
by the different control protocols as explained in Supported Kernel Execution Models in the XRT documentation. For the
sequential execution mode
ap_ctrl_hs, for example, the host
0x00000001 to the offset 0 control register
which sets Bit 0, clears Bits 1 and 2, and polls on reading
ap_done signal until it is a 1.
|0||ap_start||Asserted when the kernel can start processing data. Cleared on handshake with ap_done being asserted.|
|1||ap_done||Asserted when the kernel has completed operation. Cleared on read.|
|2||ap_idle||Asserted when the kernel is idle.|
|3||ap_ready||Asserted by the kernel when it is ready to accept the new data|
|4||ap_continue||Asserted by the XRT to allow kernel keep running|
The control register or its signals are determined by the kernel execution
ap_ctrl_none, as described in Free-Running Kernel.
The following interrupt related registers are only required if the kernel has an interrupt.
|0||Global Interrupt Enable||When asserted, along with the IP Interrupt Enable bit, the interrupt is enabled.|
|0||Interrupt Enable||When asserted, along with the Global Interrupt Enable bit, the interrupt is enabled.|
|0||Interrupt Status||Toggle on write.|