This section explains the two-step process for creating RTL kernels for the Vitis core development kit, which includes:
- Package the RTL block as a standard Vivado IP.
- Package the RTL kernel into a Xilinx Object (XO) file.
The packaged XO file is a container encapsulating the Vivado IP object (including source files) and associated kernel XML file. Using the Vitis compiler, the XO file can be combined with other kernels, and linked with the target platform and built for hardware or hardware emulation flows.