Vitis High-Level Synthesis User Guide (UG1399) - 2020.2 English

Document ID: UG1399
Release Date: 2021-03-22
Version: 2020.2 English

Revision History
Getting Started with Vitis HLS
Navigating Content by Design Process
Introduction to Vitis HLS
Basics of High-Level Synthesis
Scheduling and Binding Example
Extracting Control Logic and Implementing I/O Ports Example
Performance Metrics Example
Tutorials and Examples
Vitis HLS Process Overview
Enabling the Vivado IP Flow
Enabling the Vitis Kernel Flow
Default Settings of Vivado/Vitis Flows
Launching Vitis HLS
Setting Up the Environment
Overview of the Vitis HLS IDE
Customizing the Vitis HLS IDE Behavior
Creating a New Vitis HLS Project
Working with Sources
Coding C/C++ Functions
Accessing Source Files in Git Repositories
Using Libraries in Vitis HLS
Resolving Header File Problems
Resolving Comments in the Source Code
Setting Configuration Options
Specifying the Clock Frequency
Verifying Code with C Simulation
Writing a Test Bench
Example Test Bench
Design Files and Test Bench Files
Single File Test Bench and Design
Using the Debug Perspective
Output of C Simulation
Pre-Synthesis Control Flow
Synthesizing the Code
Synthesis Summary
Output of C Synthesis
Improving Synthesis Runtime and Capacity
Analyzing the Results of Synthesis
Schedule Viewer
Dataflow Viewer
Optimizing the HLS Project
Creating Additional Solutions
Adding Pragmas and Directives
Using Directives in Scripts vs. Pragmas in Code
Applying Directives to the Proper Scope
Applying Optimization Directives to Global Variables
Applying Optimization Directives to Class Objects
Applying Optimization Directives to Templates
Using #define with Pragma Directives
Failure to Satisfy Optimization Directives
C/RTL Co-Simulation in Vitis HLS
Output of C/RTL Co-Simulation
Automatically Verifying the RTL
Interface Synthesis Requirements
Verification of DATAFLOW and DEPENDENCE
Unsupported Optimizations for Co-Simulation
Simulating IP Cores
Analyzing RTL Simulations
Viewing Simulation Waveforms
Cosim Deadlock Viewer
Debugging C/RTL Co-Simulation
Setting Up the Environment
Optimization Directives
C Test Bench and C Source Code
Exporting the RTL Design
Configuring the Vivado IP
Output of RTL Export
Archiving the Project
Running Vitis HLS from the Command Line
Vitis HLS Methodology Guide
Introduction to Methodology Guide
Vitis HLS Coding Styles
Unsupported C/C++ Constructs
System Calls
Dynamic Memory Usage
Pointer Limitations
Recursive Functions
Standard Template Libraries
Functions
Inlining Functions
Impact of Coding Style
C/C++ Builtin Functions
Loops
Variable Loop Bounds
Loop Pipelining
Imperfect Nested Loops
Loop Parallelism
Loop Dependencies
Unrolling Loops in C++ Classes
Arrays
Array Accesses and Performance
FIFO Accesses
Arrays on the Interface
Array Interfaces
FIFO Interfaces
Array Initialization
Implementing ROMs
Data Types
Arbitrary Precision (AP) Data Types
Advantages of AP Data Types
Overview of Arbitrary Precision Integer Data Types
Overview of Arbitrary Precision Fixed-Point Data Types
Standard Types
Floats and Doubles
Composite Data Types
Structs
Structs on the Interface
Struct Padding and Alignment
Enumerated Types
Unions
Type Qualifiers
Volatile
Statics
Const
ROM Optimization
Global Variables
Pointers
Pointers on the Interface
Basic Pointers
Pointer Arithmetic
Multi-Access Pointers on the Interface
Understanding Volatile Data
Modeling Streaming Data Interfaces
Multi-Access Pointers and RTL Simulation
Vector Data Types
C++ Classes and Templates
Global Variables and Classes
Templates
Using Templates to Create Unique Instances
Assertions
Examples of Hardware Efficient C++ Code
Typical C++ Code for a Convolution Function
Horizontal Convolution
Vertical Convolution
Border Pixels
Ensuring the Continuous Flow of Data and Data Reuse
Using HLS Streams for Streaming Data
Horizontal Convolution
Vertical Convolution
Border Pixels
Summary of C++ for Efficient Hardware
Managing Interface Synthesis
Introduction to Interface Synthesis
Block and Port Interface Protocols
Clock and Reset Ports
Default Interfaces for Vivado IP Flow
Default Interfaces for Vitis Kernel Flow
Details of Interface Synthesis
Specifying Interfaces
AXI Adapter Interface Protocols
AXI4-Lite Interface
S_AXILITE Example
S_AXILITE Control Register Map
S_AXILITE and Port-Level Protocols
S_AXILITE Bundle Rules
S_AXILITE Offset Option
C Driver Files
C Driver Files and Float Types
Controlling Hardware
Controlling Software
Control Clock and Reset in AXI4-Lite Interfaces
Customizing AXI4-Lite Slave Interfaces in IP Integrator
AXI4 Master Interface
Offset and Modes of Operation
Controlling the Address Offset in an AXI4 Interface
M_AXI Bundles
Controlling AXI4 Burst Behavior
Automatic Port Width Resizing
Creating an AXI4 Interface with 32-bit Address Capability
Customizing AXI4 Master Interfaces in IP Integrator
AXI4-Stream Interfaces
How AXI4-Stream is Implemented
How AXI4-Stream Works
Registered AXI4-Stream Interfaces
AXI4-Stream Interfaces without Side-Channels
AXI4-Stream Interfaces with Side-Channels
Port-Level I/O Protocols
Port-Level I/O: No Protocol
Port-Level I/O: Wire Handshakes
Port-Level I/O: Memory Interface Protocol
Block-Level I/O Protocols
Managing Interfaces with SSI Technology Devices
Optimization Techniques in Vitis HLS
Controlling the Reset Behavior
Initialization Behavior
Initializing and Resetting Arrays
Optimizing for Throughput
Function and Loop Pipelining
Rewinding Pipelined Loops for Performance
Flushing Pipelines
Automatic Loop Pipelining
Unrolling Loops to Improve Pipelining
Addressing Failure to Pipeline
Static Variables
Partitioning Arrays to Improve Pipelining
Automatic Array Partitioning
Managing Pipeline Dependencies
Removing False Dependencies to Improve Loop Pipelining
Scalar Dependencies
Exploiting Task Level Parallelism: Dataflow Optimization
Canonical Forms
Canonical Body
Dataflow Checking
Dataflow Optimization Limitations
Configuring Dataflow Memory Channels
Specifying Arrays as Ping-Pong Buffers or FIFOs
Specifying Compiler-Created FIFO Depth
Stable Arrays
Using ap_ctrl_none Inside the Dataflow
Optimizing for Latency
Using Latency Constraints
Merging Sequential Loops to Reduce Latency
Flattening Nested Loops to Improve Latency
Optimizing for Area
Data Types and Bit-Widths
Function Inlining
Array Reshaping
Function Instantiation
Controlling Hardware Resources
Limiting the Number of Operators
Controlling Hardware Implementation
Optimizing Logic
Inferring Shift Registers
Controlling Operator Pipelining
Optimizing Logic Expressions
Optimizing Burst Transfers
Preconditions and Limitations of Burst Transfer
Options for Controlling AXI4 Burst Behavior
Examples of Recommended Coding Styles
Summary
Adding RTL Blackbox Functions
Using the RTL Blackbox Wizard
C++ Model and Header Files
RTL IP Definition
JSON File for RTL Blackbox
Vitis HLS Command Reference
vitis_hls Command
Project Commands
add_files
close_project
close_solution
cosim_design
cosim_stall
create_clock
csim_design
csynth_design
delete_project
delete_solution
enable_beta_device
export_design
get_clock_period
get_clock_uncertainty
get_files
get_part
get_project
get_solution
get_top
help
list_part
open_project
open_solution
open_tcl_project
set_clock_uncertainty
set_part
set_top
Configuration Commands
config_array_partition
config_compile
config_dataflow
config_debug
config_export
config_interface
config_op
config_rtl
config_schedule
config_storage
config_unroll
Optimization Directives
set_directive_aggregate
set_directive_allocation
set_directive_array_partition
set_directive_array_reshape
set_directive_bind_op
set_directive_bind_storage
set_directive_dataflow
set_directive_dependence
set_directive_disaggregate
set_directive_expression_balance
set_directive_function_instantiate
set_directive_inline
set_directive_interface
set_directive_latency
set_directive_loop_flatten
set_directive_loop_merge
set_directive_loop_tripcount
set_directive_occurrence
set_directive_pipeline
set_directive_protocol
set_directive_reset
set_directive_shared
set_directive_stable
set_directive_stream
set_directive_top
set_directive_unroll
HLS Pragmas
pragma HLS aggregate
pragma HLS allocation
pragma HLS array_partition
pragma HLS array_reshape
pragma HLS bind_op
pragma HLS bind_storage
pragma HLS dataflow
pragma HLS dependence
pragma HLS disaggregate
pragma HLS expression_balance
pragma HLS function_instantiate
pragma HLS inline
pragma HLS interface
pragma HLS latency
pragma HLS loop_flatten
pragma HLS loop_merge
pragma HLS loop_tripcount
pragma HLS occurrence
pragma HLS pipeline
pragma HLS protocol
pragma HLS reset
pragma HLS shared
pragma HLS stable
pragma HLS stream
pragma HLS top
pragma HLS unroll
Vitis HLS C Driver Reference
AXI4-Lite Slave C Driver Reference
X<DUT>_Initialize
X<DUT>_CfgInitialize
X<DUT>_LookupConfig
X<DUT>_Release
X<DUT>_Start
X<DUT>_IsDone
X<DUT>_IsIdle
X<DUT>_IsReady
X<DUT>_Continue
X<DUT>_EnableAutoRestart
X<DUT>_DisableAutoRestart
X<DUT>_Set_ARG
X<DUT>_Set_ARG_vld
X<DUT>_Set_ARG_ack
X<DUT>_Get_ARG
X<DUT>_Get_ARG_vld
X<DUT>_Get_ARG_ack
X<DUT>_Get_ARG_BaseAddress
X<DUT>_Get_ARG_HighAddress
X<DUT>_Get_ARG_TotalBytes
X<DUT>_Get_ARG_BitWidth
X<DUT>_Get_ARG_Depth
X<DUT>_Write_ARG_Words
X<DUT>_Read_ARG_Words
X<DUT>_Write_ARG_Bytes
X<DUT>_Read_ARG_Bytes
X<DUT>_InterruptGlobalEnable
X<DUT>_InterruptGlobalDisable
X<DUT>_InterruptEnable
X<DUT>_InterruptDisable
X<DUT>_InterruptClear
X<DUT>_InterruptGetEnabled
X<DUT>_InterruptGetStatus
Vitis HLS Libraries Reference
Arbitrary Precision Data Types Library
Using Arbitrary Precision Data Types
Arbitrary Integer Precision Types with C++
Arbitrary Precision Fixed-Point Data Types
Fixed-Point Identifier Summary
Example Using ap_fixed
C++ Arbitrary Precision Integer Types
C++ Arbitrary Precision Integer Types: Reference Information
C++ Arbitrary Precision Types
Compiling ap_[u]int<> Types
Declaring/Defining ap_[u] Variables
Initialization and Assignment from Constants (Literals)
Support for Console I/O (Printing)
Expressions Involving ap_[u]<> types
Class Methods and Operators
Other Class Methods, Operators, and Data Members
C++ Arbitrary Precision Fixed-Point Types
Fixed-Point Identifier Summary
C++ Arbitrary Precision Fixed-Point Types: Reference Information
C++ Arbitrary Precision Fixed-Point Types
ap_[u]fixed Representation
Quantization Modes
Overflow Modes
Compiling ap_[u]fixed<> Types
Declaring and Defining ap_[u]fixed<> Variables
Initialization and Assignment from Constants (Literals)
Support for Console I/O (Printing)
Expressions Involving ap_[u]fixed<> types
Class Methods, Operators, and Data Members
Vitis HLS Math Library
HLS Math Library Accuracy
HLS Math Library
Fixed-Point Math Functions
Verification and Math Functions
Verification Option 1: Standard Math Library and Verify Differences
Verification Option 2: HLS Math Library and Validate Differences
Verification Option 3: HLS Math Library File and Validate Differences
Common Synthesis Errors
HLS Stream Library
C Modeling and RTL Implementation
Global and Local Streams
Using HLS Streams
Blocking Reads and Writes
Blocking Write Methods
Blocking Read Methods
Non-Blocking Reads and Writes
Non-Blocking Writes
Fullness Test
Non-Blocking Read
Emptiness Test
Controlling the RTL FIFO Depth
C/RTL Co-Simulation Support
HLS IP Libraries
FFT IP Library
FFT Static Parameters
FFT Struct Parameters
FFT Struct Parameter Values
FFT Runtime Configuration and Status
Using the FFT Function
FIR Filter IP Library
FIR Static Parameters
FIR Struct Parameters
FIR Struct Parameter Values
Using the FIR Function
Optional FIR Runtime Configuration
DDS IP Library
DDS Static Parameters
DDS Struct Parameter Values
SRL IP Library
Mapping Directly into SRL Resources
Read from the Shifter
Read, Write, and Shift Data
Read, Write, and Enable-Shift
Vitis HLS Migration Guide
Migrating to Vitis HLS
HLS Behavioral Differences
Default Interfaces
Vitis Flow (Accelerator Mode)
Vivado Design Flow
Structs
Interface Bundle Rules
S_AXI Lite
MAXI
Interface Offset
SAXI Lite
MAXI Offset
Memory Property on Interface
AXI4-Stream Interfaces with Side-Channels
Behavior Changes to config_rtl -module_auto_prefix
Dataflow
Default User Control Settings
Unsupported Features
Pragmas
Top-Level Function Argument
HLS Video Library
C Arbitrary Precision Types
Deprecated and Unsupported Tcl Command Options
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Please Read: Important Legal Notices

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