Block and Port Interface Protocols - 2020.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
Release Date
2021-03-22
Version
2020.2 English

Block-Level Control Protocols

Block-level interface protocols provide a mechanism for controlling the operation of the Vivado IP or Vitis kernel from other RTL modules, from software applications or drivers, or from the Xilinx Run Time (XRT) in the Vitis Application Acceleration Development flow. Port-level interface protocols provide a similar mechanism for controlling the flow of data through individual ports on the IP or kernel. The specified protocols are keywords directing the HLS tool as to which protocol to implement when generating the RTL output.

Vitis HLS uses block-level control protocols ap_ctrl_chain, ap_ctrl_hs, and ap_ctrl_none to specify if the RTL is implemented with block-level handshake signals, and what signals to include. Block-level handshake signals specify the following:

  • When the design can start to perform the operation
  • When the operation ends
  • When the design is idle and ready for new inputs

By default, Vitis HLS adds a block-level interface protocol to the synthesized design to control the block. The ports of a block-level interface control when the block can start processing data (ap_start), indicate when it is ready to accept new inputs (ap_ready), and indicate if the design is idle (ap_idle) or has completed operation (ap_done). These are discussed in detail in Block-Level I/O Protocols.

Port-Level Control Protocols

Port-level I/O protocols are control signals assigned to the data ports of the Vivado IP or Vitis kernel. The I/O protocol created depends on the type of C/C++ argument and on the target flow. While block-level protocols control when the kernel is started and when it can accept data, the port-level I/O protocols are used to control the flow of data through specific ports.

Port-level protocols come in a variety of standards implemented to support the different designs and applications supported by Xilinx devices. For example, by default in the Vivado IP flow input pointers and pass-by-value arguments are implemented as simple wire ports with no associated handshaking signal, indicated by port protocol ap_none. Output pointers are implemented with an associated signal to indicate when the data is valid, using interface mode ap_vld.

Tip: It is always a good idea to specify a port protocol on an output.

As described in Default Interfaces for Vitis Kernel Flow, AXI4 interfaces are the default. The m_axi interface mode specifies an AXI4 master I/O protocol for arrays and pointers (and references in C++) only. The s_axilite interface mode specifies an AXI4-Lite slave I/O protocol for most other types. However, the ports assigned to these interfaces can also have port protocols to indicate when data is valid and when it has been consumed. Additional details are provided in Port-Level I/O Protocols.