Exporting the RTL Design - 2020.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID

UG1399

Release Date

2021-03-22

Version

2020.2 English

The final step in the Vitis HLS design flow is to package and export the RTL output. Click the Export RTL toolbar button or click Solution > Export RTL to open the Export RTL dialog box shown in the following figure.

Figure 1. Export RTL Dialog Box

The final step in the Vitis HLS flow is to export the RTL design in a form that can be used by other tools in the Xilinx design flow. The RTL design can be packaged into the following output formats:

Table 1. RTL Export Selections
Format Selection	Subfolder	Comments
Vivado IP (.zip)	`solution/impl/export.zip`	The IP is exported as a ZIP file that can be added to the Vivado IP catalog. The `impl/ip` folder also contains the contents of the unzipped IP.
Vitis Kernel (.xo)	`solution/impl/export.xo`	The XO file output can be used for linking by the Vitis compiler in the application acceleration development flow. You can link the Vitis kernel with other kernels, and the target accelerator card, to build the xclbin file for your accelerated application.
Synthesized Checkpoint (.dcp)	`solution/impl/ip`	This option creates Vivado checkpoint files which can be added directly into a design in the Vivado Design Suite. This option requires RTL synthesis to be performed. When this option is selected, the `flow` option with setting `syn` is automatically selected. The output includes an HDL wrapper you can use to instantiate the IP into a higher level design.
Vivado IP for System Generator	`solution/impl/ip`	This option creates IP for use with the Vivado edition of System Generator for DSP.

Tip: When Vitis HLS reports the results of the high-level synthesis, it provides an estimate of the results with projected clock frequencies and resource utilization (LUTs, DSPs, BRAMs, etc.). These results are merely estimates because Vitis HLS cannot know what optimizations or routing delays will be, and therefore does not know the actual area and timing values. Choosing to run Vivado synthesis or implementation provides greater accuracy of the final IP, and also makes those results available in other parts of the design flow.

Finally, you can also specify the output location to write the export file to. If the location is not specified, the default location is the solution/impl/ folder of the project.