The parameters of the software functions defined in a Vitis HLS design are synthesized into ports in the
RTL code. The parameters of the top-level function are synthesized into interfaces
and ports that group multiple signals to encapsulate the communication protocol
between the HLS design and things external to the design. Vitis HLS defines interfaces automatically, using industry standards
to specify the protocol used. The type of interfaces that Vitis HLS creates depends on the data type and direction of the
parameters of the top-level function, the target flow for the active solution, the
default interface configuration settings as specified by
config_interface
, and any specified INTERFACE pragmas or directives.
- The Vivado IP flow which is the default flow for the tool
- The Vitis Kernel flow for the Vitis Application Acceleration Development flow
open_solution -flow_target [vitis | vivado]The interface provides channels for data from outside the IP or kernel to flow into or out of the design. Data can flow from a variety of sources external to the kernel, such as a host application, an external camera or sensor, or from another kernel or IP implemented on the Xilinx device. However, the interface also provides a control scheme for the IP or kernel to be used in the operation of the block as a unit, and to manage the flow of data across a specific channel or port. These control signals are defined by the block protocol and the port protocol as explained in Block and Port Interface Protocols. The interface defines the size and performance characteristics of the data channel into the hardware design, controls the flow of data through the channels, and also controls the operation of the block.
You can see that the choice and configuration of interfaces is a key to the success of your design. However, Vitis HLS tries to simplify the process by selecting default interfaces for the target flows. For more information on the defaults used refer to Default Interfaces for Vivado IP Flow or Default Interfaces for Vitis Kernel Flow as appropriate to your design.
After synthesis completes you can review the mapping of the software arguments of your C/C++ code to hardware ports or interfaces in the SW I/O Information section of the Synthesis Summary report.