Description
Sets the default options for micro-architecture binding of an operator (add, mul, sub...) to an FPGA implementation resource, and specify its latency.
Binding is the process in which operators (such as addition,
multiplication, and shift) are mapped to specific RTL implementations. For example,
a mult operation implemented as a combinational or
pipelined RTL multiplier.
This command can be used multiple times to configure the default
binding of different operation types to different implementation resources, or
specify the default latency for that operation. The default configuration defined by
config_op can be overridden by specifying the
BIND_OP pragma or directive for a specific design element.
Syntax
config_op [OPTIONS] <op>-
<op> - Specifies the type of operation for the specified variable.
Supported values include:
mul,add,sub,fadd,fsub,fdiv,fexp,flog,fmul,frsqrt,frecip,fsqrt,dadd,dsub,ddiv,dexp,dlog,dmul,drsqrt,drecip,dsqrt,hadd,hsub,hdiv,hmul,hsqrt.
Options
-
-impl [dsp | fabric | meddsp | fulldsp | maxdsp | primitivedsp | all] - Defines the device resource to use in binding the specified operation. The default is all implementations to let the tool choose which one to use.
-
-latency <value> - Defines the default latency for the binding of the type to
the implementation resource. The valid value range varies for each
implementation (
-impl) of the operation. The default is -1, which applies the standard latency for the implementation resource.Tip: The latency can be specified for a specific operation without specifying the implementation detail. This leaves Vitis HLS to choose the implementation while managing the latency.
Examples
The following example binds the addition operation to the fabric, with the specified latency:
config_op add -impl fabric -latency 2