The Model Composer Hub block is a member of the Tools blockset within the Xilinx® Model Composer library. You can add it to your model just like any other block, by dragging it from the Library Browser onto the canvas of the Simulink® Editor. The Model Composer Hub block is a virtual block in Simulink® terms. It does not provide a physical purpose in the design, but rather provides directives for the compilation and output of the design.
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Code Generation tab
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Code directory: Defines the
output folder where the compiled results will be written. The output generated by
Model Composer can include a number of folders and files, which will all be written
into the specified directory. The folder can be specified as an absolute path (e.g.,
C:/Data/Code), or a path relative to the current Model Composer model (e.g.,
./code).Important: On the Windows operating system, you cannot specify a Target Directory name with a space in it.
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Subsystem name: Specifies the
name of the Model Composer subsystem located in the top-level of the model that is
required to generate output. Refer to Creating a Top-Level Subsystem Module for more information. The subsystem should also have an
Interface Specification block as discussed in Defining the Interface Specification. The subsystem name determines the name of the generated
output files (e.g., <subsystem_name>.cpp,<subsystem_name>.h).Tip: The Interface Spec block is not required to generate output, but it is recommended in order to have full control over the interface specification of the design.
- Target: Select one of the available output products from Model Composer. These include AI Engine code, packaged IP to add to the Vivado Design Suite IP catalog, System Generator blocks for use in RTL level block design, and C++ code for use in Vitis HLS.
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Create and run testbench:
When enabled this checkbox causes a simulation testbench to be created and launched
for the output code. The simulation compares the "golden" results from Simulink with the results obtained from the newly
compiled design. Refer to Simulating and Verifying Your Design for more
information.
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Testbench stack size:
When Create and execute testbench is
enabled, this option specifies the size, in Megabytes, of the testbench stack
frame used during C simulation (CSIM).Tip: Occasionally, the default stack frame size of 10 MB allocated for execution of the testbench may be insufficient to run the test, due to large signals arrays allocated on the stack and deep nesting of sub-systems. Typically when this happens, the test would fail with a segmentation fault and an associated error message. In such cases you may increase the size of the stack frame and re-run the test.
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Testbench stack size:
When Create and execute testbench is
enabled, this option specifies the size, in Megabytes, of the testbench stack
frame used during C simulation (CSIM).
- Generate: Compiles and writes the output from the Model Composer model.
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Code directory: Defines the
output folder where the compiled results will be written. The output generated by
Model Composer can include a number of folders and files, which will all be written
into the specified directory. The folder can be specified as an absolute path (e.g.,
C:/Data/Code), or a path relative to the current Model Composer model (e.g.,
./code).
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Hardware tab
- Project device: Defines the current target part or board platform for the Model Composer model.
- Browse button (…): Displays the Device Chooser dialog box. Refer to Device Chooser Dialog Box for more information.
- FPGA Clock Frequency (MHz): Specifies the clock frequency in MHz for the Xilinx device. This frequency is passed to the downstream tool flow.
- Throughput Factor: Specifies the data throughput requirement for the application, effecting the amount of data resources used in implementing the function in hardware.
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Feedback tab
- Connect: You can provide feedback on the Xilinx Model Composer tool, highlight problems or difficulties, suggest enhancements to the tool, or recommend new blocks for the Model Composer library.
When you have specified the target directory, the subsystem module, and the export type, you are ready to click the Generate and Run button to create the specified output. In addition to producing the C++ code, Model Composer generates the files needed to verify the code, and the necessary directives to synthesize the high-level code into RTL.