This block is used to connect the output ports
of HDL blocks to the input ports of AI Engine blocks
using the AXI4-Stream protocol.
Library
AI Engine/Interfaces
Description
This block provides an interface between the HDL and AI Engine
blocks.
- Input to the HDL to AIE block is
tdatawhich is the primary input for the data. Thetvalidsignal indicates that the producer has valid data. - Output from the HDL to AIE block is a variable size signal (data) to
AI Engine blocks along with the
treadysignal which indicates that the consumer can accept a transfer. A transfer takes place when bothtvalidandtreadyare asserted.
Parameters
- Output Data Type
- The following table shows the Output data types that are supported by the
HDL to AIE blocks and the corresponding input data type to the block.
Output Data Type Input to HDL - AIE Block int8 uint32, ufix64, ufix128 uint8 uint32, ufix64, ufix128 int16 uint32, ufix64, ufix128 uint16 uint32, ufix64, ufix128 cint16 uint32, ufix64, ufix128 int32 int32, ufix64, ufix128 uint32 uint32, ufix64, ufix128 cint32 ufix64, ufix128 x_sfix64 sfix64 x_ufix64 ufix64, ufix128 float uint32, ufix64, ufix128 float(c) ufix64, ufix128 - Output Sample Time
- This parameter depends on the initiation interval of the System Generator
design and input size to the AI Engine block (number of
cycles before the AI Engine design can consume the
frame).Note: Refer to the User Guide and product examples for more information.
- Samples per output frame
- This determines the number of samples to be queued in the buffer before the block updates the frame.
- Tready Sample time
- This should be the same as the System Generator sample time.