System Generator is a system-level modeling tool that facilitates FPGA hardware design. It extends Simulink® in many ways to provide a modeling environment that is well suited to hardware design. The tool provides high-level abstractions that are automatically compiled into an FPGA at the push of a button. The tool also provides access to underlying FPGA resources through low-level abstractions, allowing the construction of highly efficient FPGA designs.
| Design Flows Using System Generator | Describes several settings in which constructing designs in System Generator is useful. |
| System-Level Modeling in System Generator | Discusses System Generator's ability to implement device-specific hardware designs directly from a flexible, high-level, system modeling environment. |
| Automatic Code Generation | Discusses automatic code generation for System Generator designs. |
| Compiling MATLAB into an FPGA | Describes how to use a subset of the MATLAB programming language to write functions that describe state machines and arithmetic operators. Functions written in this way can be attached to blocks in System Generator and can be automatically compiled into equivalent HDL. |
| Importing a System Generator Design into a Bigger System | Discusses how to take the VHDL netlist from a System Generator design and synthesize it in order to embed it into a larger design. Also shows how VHDL created by System Generator can be incorporated into a simulation model of the overall system. |
| Configurable Subsystems and System Generator | Explains how to use configurable Subsystems in System Generator. Describes common tasks such as defining configurable Subsystems, deleting and adding blocks, and using configurable Subsystems to import compilation results into System Generator designs. |
| Notes for Higher Performance FPGA Design | Suggests design practices in System Generator that lead to an efficient and high-performance implementation in an FPGA. |
| Using FDATool in Digital Filter Applications | Demonstrates one way to specify, implement and simulate a FIR filter using the FDATool block. |
| Multiple Independent Clocks Hardware Design | The design can be partitioned into groups of Subsystem blocks, where each Subsystem has a common cycle period, independent of the cycle period of other Subsystems. |
| AXI Interface | Provides an introduction to AMBA AXI4 and draws attention to AMBA AXI4 details with respect to System Generator. |
| AXI4-Lite Slave Interface Generation | Describes features in System Generator that allow you to create a standard AXI4-Lite interface for a System Generator module and then export the module to the Vivado® IP catalog for later inclusion in a larger design using IP integrator. |
| Tailor Fitting a Platform Based Accelerator Design in System Generator | Describes how to develop an accelerator in System Generator which is part of a platform framework developed in the Vivado IP Integrator. |