Interconnecting AI Engine and HDL Blocks - 2020.2 English

The HDL blockset in the Xilinx® toolbox contains the common DSP building blocks such as adders, multipliers, and registers. It also includes a set of complex DSP building blocks such as FFTs, filters and memories. System Generator automatically compiles designs into low-level representations (i.e., RTL) which can be targeted to programmable logic. The Versal hardware allows for connecting AI Engine kernels and PL kernels. However, System generator and AI Engine domains are incompatible in at least two aspects:

• The System Generator domain is cycle accurate, whereas the AI Engine domain is only bit accurate. A System Generator design may cause back pressure or may not have a valid output and these are managed through designs with Tvalid and Tready signals of AXI Stream ports.
• System Generator accepts only scalar inputs, whereas AI Engine blocks work with variable sized vector signals.

To account for the above, Model Composer provides interface blocks in the AI Engine library to connect from AI Engine to HDL blocks and vice-versa.

• AIE to HDL - This block connects AI Engine to HDL blocks using an AXI4-Stream-like interface.
• HDL to AIE - This block connects HDL to AXI4-Stream blocks using AXI4-Stream-like interface.

You can find these blocks in Xilinx Toolbox/AI Engines/Interfaces library.

As discussed, AIE-HDL and HDL-AIE blocks have Tvalid and Tready ports as depicted in the previous figure. The gateway from the AI Engine to the HDL domain performs the unbuffer operation, meaning that the HDL domain will run at a different rate than the AI Engine domain. For example, if the AI Engine domain is producing 16 samples at every clock, the HDL domain must run at least 16 times faster to process the data. However, in some cases, the HDL domain needs to run even faster because the HDL domain, being a cycle accurate domain, may not consume one sample per clock. For example, if the HDL domain consumes one sample every two clocks, (initiation interval of 2), for the earlier example, the HDL domain needs to run 32 times faster than the AI Engine domain.

The following section discusses block parameters of AIE to HDL and HDL to AIE blocks and includes examples.