Control implementation of the model
Description
The Model Composer Hub block controls the behavior of the Xilinx® Model Composer tool.
You can specify the targeted design flow for the generated output, the directory path for the output, and the desired device and design clock frequency using the following tabs.
- The Code Generation tab provides options to select the output flow through Export type, the code generation directory, and test bench generation.
- The Hardware tab helps with device or board selection. You can specify clock frequency and throughput factor for the model.
- The Feedback tab is used to provide feedback to the tool developers, and suggestions to improve the tool.
Library
Tools
Data Type Support
Data type support is not applicable to the Model Composer Hub block.
Parameters
- Code Generation tab
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- Subsystem name
- Enter a subsystem name that contains only Model Composer blocks.
- Code directory
- Enter the output directory name with the complete path, or use the Browse button to provide a path.
- Target
-
Target settings are shown in the following table.
Table 1. Target Settings Setting Description IP Catalog Select IP Catalog to export the design to the Vivado IP Catalog. After C/C++ code generation, Vivado High-Level Synthesis (HLS) is invoked to synthesize the C code and create a project that can be exported as an IP to the Vivado IP Catalog.
System Generator Select System Generator to export the design to System Generator. After C/C++ code generation, Vivado High-Level Synthesis (HLS) is invoked to synthesize the C code and create an RTL solution that can be used as a Vitis HLS block in a System Generator model. HLS C++ code Select HLS C++ code to compile the design model into C++ code. AI Engine This is the default selection. AI Engine-specific options are:- Compiler options
- This option provides control over compiler debug options, execution target options etc.
- Create testbench
- When selected, Model Composer generates the test vectors while generating the code.
- Run Cycle-accurate SystemC Simulator
- This option is only available if Create testbench is selected. When enabled, it runs the AI Engine SystemC simulation after code generation.
- Launch Vitis Analyzer
- When selected, Model Composer invokes Vitis Analyzer to analyze the reports after running AI Engine SystemC simulation.
- Create and execute testbench
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If selected, Model Composer runs simulation and generates test vectors while generating code.Important: This option is not available when the target is AI Engine.
- Testbench stack size
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This parameter prompts you to enter a larger stack size.
When Create and execute testbench is enabled, the Testbench stack size option specifies the size of the testbench stack frame during C simulation (CSIM). Occasionally, the default stack frame size of 10 MB allocated for execution of the testbench may be insufficient to run the test, due to large arrays allocated on the stack and/or deep nesting of sub-systems. Typically when this happens, the test would fail with a segmentation fault and an associated error message. In such a case you may opt to increase the size of the stack frame and rerun the test.
- Hardware tab
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- Project device
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Specifies the current target part or board platform for the Model Composer model.
Clicking the browse button (…) next to Project device displays the Device Chooser dialog box, which allows you to select the board or part to which your design is targeted. Xilinx Model Composer obtains board and device data from the Vivado Design Suite database.
- FPGA clock frequency
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Specifies the clock frequency in MHz for the Xilinx device. This frequency is passed to the downstream tool flow.
- Throughput factor
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Specifies the number of samples processed per clock to increase the throughput. A larger factor increases hardware resource usage. The throughput factor must be between 1 and 16.
- Feedback tab
- This tab requests feedback to the tool developers, and suggestions to improve the tool. It points to a weblink that opens a survey that can be completed in less than 3 minutes.