If you focus all your optimization efforts using the back-end implementation tools, you may not be able to achieve timing closure because of the following reasons:
- The more complex IP blocks in a System Generator design like FIR Compiler and FFT are generated under the hood. They are provided as highly-optimized netlists to the synthesis tool and the implementation tools, so further optimization may not be possible.
- System Generator netlisting produces HDL code with many instantiated primitives such as registers, BRAMs, and DSP48E1s. There is not much a synthesis tool can do to optimize these elements.
The following tips focus on what you can do in System Generator to increase the performance of your design before you start the implementation process.