Specifying PLIOs in Model Composer designs - 2020.2 English

Model Composer supports specifying the PLIO width using the AIE Signal Spec block and making external stream connections that cross the AI Engine to PL boundary.

Figure 1. AIE Signal Spec

The AIE Signal Spec block supports specifying the hardware platform I/O properties at the boundary of the AI Engine subsystem, along with the FIFO depth information as discussed in Stream FIFO Depth Specification.

Figure 2. Block Parameters: AIE Signal Spec

From the Platform I/O tab in the AIE Signal Spec block, you can select the available PLIO width options from the drop-down menu.

Consider following example where an AIE Signal Spec block is connected at the boundary of the AI Engine subsystem.

Figure 3. AIE Signal Spec Block Connected to AI Engine Subsystem

By default, the PLIO width is set to auto. Other available options are: 32, 64, and 128.

Figure 4. Block Parameters: AIE Signal Spec PLIO Width

After the PLIO width is specified as 64 and 128 for the two AIE Signal Spec blocks in the example, the GUI updates as follows.

Figure 5. AIE Signal Spec Blocks Updated

#include "DUT.h"
 
// Mapping inputs to PLIO
adf::PLIO in1("PL_AIE_IN", adf::plio_64_bits, "PL_AIE_IN.txt");
 
// Mapping outputs to PLIO
adf::PLIO out1("AIE_PL_OUT", adf::plio_128_bits, "AIE_PL_OUT.txt");
 
// instantiate cardano dataflow graph
DUT mygraph;
 
// connect dataflow graph to simulation platform
adf::simulation::platform<1,1> platform(&in1, &out1);