To ensure that the HDL files generated by System Generator work correctly in hardware, you must close timing. To help accelerate this process, timing analysis has been integrated into System Generator.
Timing analysis allows you to perform static timing analysis on the HDL files generated from System Generator, either Post-Synthesis or Post-Implementation. It also provides a mechanism to correlate the results of running the Vivado® Timing Engine on either the Post-Synthesized netlist or the Post Implementation netlist with the System Generator model in Simulink® . Thus, you do not have to leave the Simulink® modeling environment to close timing on the DSP sub-module of the design.
Invoking timing analysis on a compilation target (for example, HDL Netlist) results in a tabulated display of paths with columns showing information such as timing slack, path delay, etc. This is the Timing Analyzer table. You can sort the contents of the table using any of the column metrics such as slack, etc. Also, cross probing is enabled between the table entries and the Simulink model to accelerate finding and fixing timing failures in the model. Cross probing between the Timing Analyzer table and the Simulink model is accomplished by selecting/clicking a row in the table. The corresponding path in the model will be highlighted. The path is highlighted in red if the path corresponds to a timing violation; otherwise it is highlighted in green.