In this lab, you will learn how AXI interfaces are implemented using System Generator. You will save the design in IP catalog format and use the resulting IP in the Vivado® IP integrator environment. Then you will see how IP integrator enhances your productively by supplying connection assistance when you use AXI interfaces.
After completing this lab, you will be able to:
- Implement AXI interfaces in your designs.
- Add your design as IP in the Vivado IP catalog.
- Connect your design in IP integrator.
This lab has four primary parts:
- In Step 1, you will review how AXI interfaces are implemented using System Generator.
- In Step 2, you will create a Vivado project for your System Generator IP.
- In Step 3, you will create a design in IP integrator using the System Generator IP.
- In Step 4, you will implement the design and generate an FPGA bitstream (the file used to program the FPGA).