Step 2: Creating Asynchronous Channels - 2020.2 English

Vivado Design Suite Tutorial: Model-Based DSP Design using Add-on for MATLAB and Simulink (UG1498)
Document ID
UG1498
Release Date
2021-01-22
Version
2020.2 English
In this step you will implement asynchronous channels between subsystems using FIFOs. The data in FIFOs operates on a First-In-First-Out (FIFO) basis, and control signals ensure data is only read when valid data is present and data is only written when there is space available. If the FIFO is empty or full the control signals will stall the system. In this design the inputs will always be capable of writing and there is no requirement to consider the case for the FIFO being full.
There are two data paths in the design where FIFOs are required:
  • Data from CTRL to Gain Control.
  • Data from DDC to Gain Control.
  1. Right-click anywhere in the canvas and select Xilinx BlockAdd.
  2. Type FIFO in the Add Block dialog box.
  3. Select FIFO from the menu to add a FIFO to the design.
  4. Connect the data path through instance FIFO. Delete any existing connections to complete this task.
    1. Connect CTRL/Out1 to FIFO/din.
    2. Connect FIFO/dout to Gain Control/In1.
  5. Make a copy of the FIFO instance (using Ctrl-C and Ctrl-V to copy and paste).
  6. Connect the data path through instance FIFO1. Delete any existing connections to complete this task.
    1. Connect DDC/Out2 to FIFO1/din.
    2. Connect FIFO1/dout to Gain Control/In3.

    You have now connected the data between the different domains and have the design shown in the following figure.



    You will now connect up the control logic signals to ensure the data is safely passed between domains.

    • From the CTRL block a write enable is required. This is not currently present and needs to be created.
    • From the DDC block a write enable is required. The data_tvalid from the final FIR stage can be used for this.
    • The Gain Control must generate a read enable for both FIFOs. You will use the empty signal from the FIFOs and invert it; if there is data available, this block will read it.
  7. Double-click the CTRL block to open the subsystem.
  8. Right-click in the canvas and use Xilinx BlockAdd to add these blocks:
    1. Delay (Xilinx)
    2. Relational
  9. Select instance Out1 and make a copy (use Ctrl-C and Ctrl-V to cut and paste).
  10. Double-click the Relational block to open the Properties Editor.
  11. Use the Comparison drop-down menu to select a!=b and click OK.
  12. Connect the blocks as shown in the following figure.

    This will create an output strobe on Out2 which will be active for one cycle when the input changes, and be used as the write-enable from CTRL to the Gain Control (the FIFO block at the top level).

  13. Click the Up to Parent toolbar button to return to the top level.
  14. Double-click the instance Gain Control to open the subsystem.
  15. Right-click in the canvas and use Xilinx BlockAdd to add these blocks:
    1. Inverter
    2. Inverter (for a total of two inverters)
    3. Delay (Xilinx)
  16. Select the instance Out1 and make a copy Out3 (use Ctrl-C and Ctrl-V to cut and paste).
    • Rename Out3 to DDC_Read
  17. Select instance Out1 and make a copy Out3 (use Ctrl-C and Ctrl-V to cut and paste).
    • Rename Out3 to CTRL_Read
  18. Select instance In1 and make a copy In4 (use Ctrl-C and Ctrl-V to cut and paste).
    • Rename In4 to CTRL_Empty
  19. Connect the blocks as shown in the following figure.

    • The FIFO empty signal from the top-level Gain Control FIFO (FIFO) block is simply an inverter block used to create a read-enable for the top-level DDC FIFO (FIFO1). If the FIFO is not empty, the data will be read.
    • Similarly, the FIFO empty signal from the top-level DDC FIFO (FIFO1) is inverted to create a FIFO read-enable.
    • This same signal will be used as the new data_tvalid (which was In2). However, because the FIFO has a latency of 1, this signal must be delayed to ensure this control signal is correctly aligned with the data (which is now delayed by 1 through the FIFO).
  20. Use the Up to Parent toolbar button to return to the top level.

    This shows the control signals are now present at the top level.



    You will now complete the final connections.

  21. Connect the control path through instance FIFO. Delete any existing connections to complete this task.
    1. Connect CTRL/Out2 to FIFO/we.
    2. Connect FIFO/empty to Gain Control/CTRL_Empty.
    3. Connect Gain Control/CTRL_Read to FIFO/re.
  22. Connect the control path through instance FIFO1. Delete any existing connections to complete this task.
    1. Connect DDC/Out1 to FIFO1/we.
    2. Connect FIFO1/empty to Gain Control/In2.
    3. Connect Gain Control/DDC_Read to FIFO1/re.


  23. Click the Run simulation button to simulate the design and confirm the correct operation – you will see the same results as Step 1 action 4.
In the next step, you will learn how to specify different clock domains are associated with each hierarchy.