- Click Create Block Design
in the Flow Navigator pane.
- In the Create Block Design dialog box, click OK to accept the default name.
You will first create an IP repository for the System Generator IP, and add the IP to the repository.
- Right-click in the Diagram window, and select IP Settings.
- In the Settings dialog box, select Add Repository button () to add a repository.
under Project Settings and click the
- In the IP Repositories dialog box, navigate to the following
- With folder ip selected,
click Select to create the new repository
as shown in the following figure.
- Click OK to exit the Add Repository dialog box.
- Click OK to exit the Settings dialog box.
- Click the Add IP button in the center of the canvas.
zynqin the Search field.
- Double-click ZYNQ7 Processing
System to add the CPU.
- Click Run Block
Automation as shown in the following figure.
- Leave Apply Board Preset selected and click OK. This will ensure the design is automatically configured to operate on the ZC702 evaluation board.
- Right-click anywhere in the block diagram and select Add IP.
lab5in the Search dialog box.
- Double-click lab5_1 to
add the IP to the design.
You will now connect the IP to the rest of the design. Vivado IP integrator provides automated assistance when the design uses AXI interfaces.
- Click Run Connection Automation (at the top of the design canvas).
- Click OK to accept the default options (lab5_1_0/lab5_1_s_axi to processing_system7_0/M_AXI_GP0) and connect the AXI4-Lite interface to the Zynq®-7000 IP SoC.
- Double-click the ZYNQ7 Processing System to customize the IP.
- Click the PS-PL Configuration as shown in the following figure.
- Expand the HP Slave AXI Interface and select the S AXI HP0 interface.
Make sure to check the box next to S AXI HP0 interface.
- Click OK to add this port to the Zynq Processing System.
- On the System Generator IP
lab5_1 block, click the AXI4-Stream input
s_axis_sourceand drag the mouse. Possible valid connections are shown with green check marks as the pencil cursor approaches them. Drag the mouse to the
S_AXI_HP0port on the Zynq Processing System to complete the connection.
- Click OK in the Make Connection dialog box.
- Click Run Connection Automation to connect the AXI4-Lite interface on the AXI DMA to the processor.
- Click OK to accept the default.
- Use the Validate Design toolbar button to confirm the design has
- Click OK to close the
Validate Design message.
The design from System Generator has now been successfully incorporated into an IP integrator design. The IP in the repository can be used within any Vivado project, by simply adding the repository to the project.
- You will now process the design through to bitstream.
You will now process the design through to bitstream.