Inserting some registers in the combinational path might give better timing results and might help overcome timing violations if any. This can be done by changing latency of the combinational blocks as explained in the following.
- Double-click the violated path from the Timing Analyzer window
which opens the violated path as shown in the following figure.
- Double-click the Mult
block to open the Multiplier block parameters window as shown in the following
- Under Basic tab, change the latency from 1 to 2 and click OK.
- Double-click the System Generator token, and ensure that the Analyzer Type is Timing and click Generate.
- After the generation completes, it opens the timing Analyzer
table as shown in the following figure. Observe the status pass at the top-right
corner. It indicates there are no timing violated paths in the design.
- For quicker timing analysis iterations, post-synthesis analysis is preferred over post-implementation analysis.
- Changing the latency of the block might increase the number of resources which can be seen using Step 2: Resource Analysis in System Generator.