Hard IP Block Support for UltraScale Devices - 2020.2 English

Xilinx Power Estimator User Guide (UG440)

Document ID
UG440
Release Date
2020-12-04
Version
2020.2 English

The Hard IP Block setting allows you to calculate the power associated with the following UltraScale device integrated IP blocks:

PCIe
The integrated PCI Express core is a reliable, high-bandwidth, scalable serial interconnect. Select PCIe when using hard GEN1, GEN2, GEN3 or GEN4 PCIe interface with GTs. Select PCIe_500 when using hard GEN3 PCIe interface operating with an optional 500MHz core clock frequency.
100G Ethernet
The integrated block for 100 Gb/s Ethernet (100G MAC) provides a high performance, low latency 100 Gb/s Ethernet port that allows for a wide range of user customization and statistics gathering. If your design uses the integrated block for 100 Gb/s Ethernet, select CMAC. Select CMAC-Low when you use low data toggle rate or CMAC-High for worse case data toggle rate. For detailed information on this IP block, see the UltraScale Devices Integrated Block for 100G Ethernet LogiCORE IP Product Guide (PG165).
Interlaken
The integrated block for Interlaken is a scalable chip-to-chip interconnect protocol designed to enable the following:
  • The lane logic only mode allows each serial transceiver to be used to build a fully featured Interlaken interface. In devices with 48 serial transceivers, up to 600 Gb/s of total throughput can be sustained.
  • The protocol logic supported in each integrated IP core scales up to 150 Gb/s.

If your design uses the integrated block for Interlaken, select ILKN. Select ILKN-Low when you use low TX data toggle rate or ILKN-High for worse case data toggle rate. For detailed information on this IP block, see the Integrated Interlaken up to 150G LogiCORE IP Product Guide (PG169).

These IP blocks are designed to be combined with GTH or GTY transceivers to implement an integrated solution. You can use the Transceiver Configuration wizard to combine the appropriate GTH or GTY transceiver configuration with an integrated hard IP block.

To open the Transceiver Configuration wizard, click the Add GTH Interface button at the top of the GTH sheet.

Or click the Add GTY Interface button at the top of the GTY sheet.

For a description of the entries in the Transceiver Configuration wizard, see Using the Transceiver Configuration Wizard.

The following figure shows the Hard IP Block setting in the UltraScale device XPE spreadsheet, the transceiver power used by the Hard IP, and the utilization percentage for each type of Hard IP.

Figure 1. Hard IP Settings for UltraScale Devices