Routing Complexity is the average number of routing resources per logic cell which includes fanout, interconnect capacitance, wire length etc. The medium complexity value is 8. The high complexity value is 10 and very high complexity value is 12. Use higher values only when experiencing a higher routing congestion especially on a high performance, high utilization designs. Xilinx recommends leaving this filed at default value for early estimation, until the design complexity is known.
During the design implementation, Vivado Report Power estimates the routing complexity accurately, which can be imported into XPE to better realize the correct values for a given design. Note that the imported values for any specific logic could be higher than the default (i.e. 12), which is valid because the imported results are more elaborated to specific logic compared to manual entry based on grouping multiple blocks in a single row.