The Other sheet allows you to calculate the power associated with these device features:
(7 series and Zynq-7000 SoC only) The XADC (Xilinx Analog-to-Digital Converter) is the basic building block that enables agile mixed signal functionality in Xilinx 7 series devices. The XADC includes a dual 12-bit, 1 Mega sample per second (MSPS) ADC and on-chip sensors.
In the 7 series or Zynq-7000 SoC, the XADC can be powered down if unused, to save power. In the XADC table, set Powered Down to Yes if the XADC will be powered down by setting the power down bits in the device’s configuration register or by disconnecting the VCCADC supply. Set Powered Down to No if the XADC will not be powered down.
XADC Clock (MHz) specifies the frequency of the DRP clock if your design uses the XADC. Leave this blank if your design does not instantiate the XADC or the XADC is powered down.Note: Since XADC is on by default in the FPGA, the XADC power is reported as part of the static power.
The XADC is described in the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480).
(UltraScale and UltraScale+ devices only) The System Monitor (SYSMON) monitors the UltraScale device physical environment using on-chip temperature and supply sensors, external analog inputs, and an integrated analog to digital converter (ADC).In the UltraScale device, the SYSMON can be powered down if unused, to save power. In the SYSMON table, set Powered Down to Yes if the SYSMON will be powered down by setting the power down bits in the device configuration register or by disconnecting the VCCADC supply. Set Powered Down to No if the SYSMON will not be powered down.Note: Since SYSMON is on by default in the FPGA, the SYSMON power is reported as part of the static power
Clock (MHz) specifies the frequency of the DRP clock if your design uses the SYSMON. Leave this blank if your design does not instantiate the SYSMON or the SYSMON is powered down.
The SYSMON is described in the UltraScale Architecture System Monitor User Guide (UG580).
- The Config (Configuration) table allows you to specify these device configuration features:
- Readback CRC Clock (MHz)
Xilinx 7 series and UltraScale devices include a feature to do continuous readback of configuration data in the background of a user design. This feature is aimed at simplifying detection of Single Event Upsets (SEUs) that cause a configuration memory bit to flip and can be used with the FRAME ECC feature for advanced operations such as SEU corrections. In the Config table, enter the ReadBack CRC Clock frequency to include this feature in the XPE power estimate. Leave this blank if your design does not use the Readback CRC feature.
Readback CRC is described in the 7 Series FPGAs Configuration User Guide (UG470) or the UltraScale Architecture Configuration User Guide (UG570).
- Config Bank Voltage
Specifies the setting of the Configuration Bank Voltage Select (CFGBVS), which determines the I/O voltage operating range and voltage tolerance for the configuration-related I/O banks in the device.
Configuration bank voltage is described in the 7 Series FPGAs Configuration User Guide (UG470) or the UltraScale Architecture Configuration User Guide (UG570).
Phaser blocks are available in 7 series devices to simplify the interface with high-speed memory devices. For power estimation, these blocks are represented in a table on the Other sheet. Details for each Phaser setting are available in the Zynq-7000 SoC and Zynq-7000 SoC and 7 series Devices Memory Interface Solutions (UG586).
In the Phaser table, the Phaser INs column is used to specify the number of PHASER_IN and PHASER_IN_PHY blocks used. Similarly, the Phaser OUTs column is used for both PHASER_OUT and PHASER_OUT_PHY blocks.
A VCU (Video Codec Unit) exists in Zynq UltraScale+ EV devices. The VCU provides a multi-standard video encoding and decoding capabilities, that includes High Efficiency Video Coding (HEVC), i.e., H.265, and Advanced Video Coding (AVC), i.e., H.264 standards. The VCU is capable of simultaneous encoding and decoding video streams at rates up to 4Kx2K at 60 frames per second (fps).Other Sheet in XPE populates the VCU parameters to estimate the power consumption for the VCU block. This VCU estimator will be available when you select any Zynq UltraScale+ EV device in Summary sheet. The following figure displays the VCU Xilinx Power Estimator.Figure 1. Other Sheet Displaying the VCU Power EstimatorPower can be estimated for any combination of VCU configurations by selecting the desired parameters for the VCU block for encoder and decoder such as resolution, color format etc.Note: On the Other Sheet, the reported VCU power is only the dynamic power while on the Summary Sheet, the VCU power will include both the static and dynamic powers.
UltraScale and UltraScale+ devices have a security feature
that allows you to program eFUSE bits that force the FPGA to only
allow encrypted bitstreams during runtime. XPE allows you to
estimate the power consumption when the eFUSE is being programmed
during runtime. You must analyze the power with the eFUSE
programming image.Note: This power will not be considered for On-Chip Power computation because it is specific to eFUSE state, where the application design is not programmed.Figure 2. Other Power Sheet (7 Series Devices)