Xilinx device families have different clock generation and management capabilities. To enter information in these sheets, first review the 7 Series FPGAs Clocking Resources User Guide (UG472) or the UltraScale Architecture Clocking Resources User Guide (UG572) to understand how to parameterize these resources in XPE. Depending on the step in the project development cycle you might or might not already know all the clocking details for your design. Enter what is known or can be estimated first, then later you can always reopen and complete the spreadsheet as design details become available.
The clock management resource sheets are presented in a different way in the XPE spreadsheets that support the various FPGA and SoC architectures.
- In the 7 series/ Zynq®-7000 SoC and above devices XPE spreadsheet, information for the two clock managers, MMCM and PLL, is supplied on a single sheet, the Clock Manager Power sheet. An MMCM or PLL column in the Clock Manager Power sheet lets you specify whether you are supplying information for the MMCM or the PLL.
- In spreadsheets for earlier devices (for example, the Virtex-5/Virtex-6 spreadsheet or the Spartan-3A/Spartan-6 spreadsheet), there will be a different sheet for each clock manager used. For example, separate DCM Power and PLL Power sheets may be displayed in these earlier spreadsheets.
The following figure shows a sample clock management resource sheet (the Clock Manager Power sheet).
