The Logic sheet (see Figure 1) is used to estimate the power consumed in the CLB ower accounts for both the logic components and the routing. types of information should be entered:
- Enter the number of LUTs configured as Logic, Shift Registers and LUT-based RAMs and ROMs. If your design or a previous generation has been implemented within ISE or the Vivado Design Suite use the Import button in the Summary sheet to automatically import this information. Otherwise, use your experience to estimate usage required to implement the desired functionality.
- Enter the Clock domain this logic belongs to. Then enter the Toggle Rate the logic is expected to switch and the Average Fanout.
Tip: The default setting for Toggle Rate (12.5%) and Average Fanout (3) or Routing Complexity (8|10) are based on an average extracted from a suite of customer designs. In the absence of a better estimate for your specific design, Xilinx recommends using the default setting.
Note: The Signal Rate column defines the number of millions of transitions per second for the considered element. This is a read-only column.
Note: The specified toggle rate represents the average switching activities on both input and outputs of total logic specified in a row. When you group multiple blocks in a single row, the average toggle for the entire group is still lower even if any specific block in a design can toggle much higher.
Signal Rate is computed in the following way:
Signal Rate (Mtr/s) = Clock Frequency (MHz) * Toggle rate (%)
Figure 1. Effect of LUT Configuration, Toggle Rates, and Average Fanout on Power Estimation (7 Series Devices)
To enter information on the Logic sheet related to distributed memory, you can use the XPE Memory Generator wizard, which appears when you click the Add Memory button on the Logic sheet. The XPE Memory Generator wizard provides a simplified method of adding memory-related rows to the Logic sheet.