config_timing_analysis - 2020.2 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
UG835
Release Date
2020-11-18
Version
2020.2 English

Configure timing analysis general settings

Syntax

config_timing_analysis [‑enable_input_delay_default_clock <arg>]
    [‑enable_preset_clear_arcs <arg>] [‑ignore_io_paths <arg>]
    [‑disable_flight_delays <arg>] [‑merge_exceptions <arg>]
    [‑timing_early_launch_at_borrowing_latches <arg>]
    [‑enable_time_borrowing_for_max_delay_exceptions <arg>] [‑quiet]
    [‑verbose]

Usage

Name Description
[-enable_input_delay_default_clock] Launch SDC unclocked input delays from an internally defined clock: Values: true, false; This option is not supported for UCF constraints
[-enable_preset_clear_arcs] Time paths through asynchronous preset or clear timing arcs: true, false;
[-ignore_io_paths] Ignore paths from primary inputs and paths to primary outputs: Values: true, false
[-disable_flight_delays] Disable adding package times to IO Calculations : Values: true, false;
[-merge_exceptions] Allow/Prevent the timing engine from merging timing exceptions : Values: true, false;
[-timing_early_launch_at_borrowing_latches] Remove clock latency pessimism from the launching enable of paths through transparent latches. Values: auto, true, false Default: auto
[-enable_time_borrowing_for_max_delay_exceptions] Allow timing paths covered by set_max_delay timing exceptions to borrow time. Values: true, false
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution

Categories

Timing

Description

This command configures general features of timing analysis.

Note: This command returns nothing if successful, or returns an error if it fails.

Arguments

-enable_input_delay_default_clock [ true | false ] - (Optional) Launch un-clocked input delays from an internally defined clock for timing analysis. The valid values are true or false, with a default setting of false.

-enable_preset_clear_arcs [ true | false ] - (Optional) Enable timing paths through asynchronous preset or clear timing arcs. The valid values are true or false, with a default setting of false. By default the timing arcs of asynchronous resets are disabled in the Vivado timing engine. This option lets you enable them for timing analysis to see if problems caused by the assertion of the asynchronous reset exist in the design.

-ignore_io_paths [ true | false ] - (Optional) Ignore paths from primary inputs and paths to primary outputs. This lets you eliminate the net delay from the input port and to the output port as part of the timing path.

-disable_flight_delays [ true | false ] - (Optional) Do not add package delays to I/O calculations when this option is true.

-timing_early_launch_at_borrowing_latches [ auto | true | false ] - (Optional) Remove clock latency pessimism from the launching enable of paths through transparent latches. In an enabled latch the timing path for setup/hold calculations originates from the D pin of the latch instead of G pin. This option affects those timing paths. This option can be set to true to compensate for timing optimism when CRPR is not enabled, the Vivado timing engine uses the early launch edge from when the latch opens to calculate the launch clock latency. However, when CRPR is enabled, which is the default in the Vivado timer, this option is too conservative and should be set to false. The default setting is auto which lets the Vivado timing engine determine when to eliminate CRPR from paths through enabled latches.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

Examples

The following example ignores the package delays during timing analysis:
config_timing_analysis -disable_flight_delays true