Vivado delivers precompiled simulation libraries for use with the Vivado simulator, as well as precompiled libraries for all the static files required by Xilinx IP. When simulation scripts are created, they reference these precompiled libraries.
When using third-party simulators, you must compile Xilinx simulation libraries prior to running simulation, as explained in the Vivado Design Suite User Guide: Logic Simulation (UG900). This is especially true if your design instantiates VHDL primitives or Xilinx IP, the majority of which are in VHDL form. The simulation tool will return “library binding” failures if you do not precompile simulation libraries.
You can run the
compile_simlib Tcl command to compile the Xilinx simulation libraries for the target simulator. You can also issue
this command from the Vivado IDE by selecting .