The following are some key suggestions related to simulating in the Vivado Design Suite. Many of these tips are described in greater detail in the text that follows, or in Vivado Design Suite User Guide: Logic Simulation (UG900).
- Run behavioral simulation before proceeding with synthesis and implementation. Issues identified early will save time and money.
- Infer logic wherever possible. Instantiating primitives adds significant simulation runtime cost.
- Always set the Target Language to Mixed unless you do not have a mixed mode license for your simulator.
- Turn off the waveform viewer when not in use to improve simulation performance.
- In the Vivado simulator, turn off debug during xelab for a performance boost.
- In the Vivado simulator, turn on multi-threading to speed up compile time.
- When using third-party simulators, always target supported versions. For more information, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
- Make sure incremental compile is turned on when using third-party simulators.
- Use the Xilinx Tcl command
export_simulationto generate batch scripts for selected simulators.
- Generate simulation scripts for individual IP, BDs, and hierarchical modules as well as for the top-level design.
- If you are targeting a 7 series device, use UNIFAST libraries
to improve simulation performance.Note: The UNIFAST libraries are not supported for UltraScale device primitives.