Additional I/O pin planning steps are required when using Xilinx memory IP. After the IP is customized, you then assign the top-level I/O ports to physical package pins in either the elaborated or synthesized design in the Vivado IDE.
All of the ports associated with each memory IP are grouped together into an I/O Port Interface for easier identification and assignment. A Memory Bank/Byte Planner is provided to assist you with assigning Memory I/O pin groups to Byte lanes on the physical device pins.
For more information, see this link in the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).
If you have memory IP in your design, see the following resources: