The Vivado Design Suite is board aware and can automatically derive I/O constraints and IP configuration data from included board files. Through the board files, the Vivado Design Suite knows the various components present on the target boards and can customize and configure an IP to be connected to a particular board component. Several 7 series, Zynq-7000 SoC, and UltraScale™ device boards are currently supported. You can download support files for partner-developed boards from the partner websites or from the Xilinx XHub Store.
The IP integrator shows all the component interfaces on the target board in a separate tab called the Board tab. You can use this tab to connect to the desired components through the Designer Assistance feature. All the I/O constraints are automatically generated as a part of using this feature.
You can also generate board files for custom boards and add the repository that contains the board file to a project. For more information on generating a custom board file, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).