The Vivado Design Suite provides automated methodology checks based on the UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949) using the Report Methodology command.
You can generate a methodology report on an opened, elaborated, synthesized, or implemented design. For an elaborated design, the methodology report checks the XDC and RTL files. For information on running the methodology report using Tcl commands, see this link command in the Vivado Design Suite Tcl Command Reference Guide (UG835).
Recommended: Running the methodology report allows you to find design issues
early during the elaboration stage prior to synthesis, which saves time in the design
process. It is highly recommended that you run these checks on your design and address
any issues identified.