For detailed information on Zynq®-7000 pins, including MIO pins, see the Zynq-7000 SoC Technical Reference Manual (UG585).
For detailed information on Zynq UltraScale+ MPSoC pins, including MIO pins, see Zynq UltraScale+ Device Technical Reference Manual (UG1085)
To configure a port or a group of ports:
- In the I/O Ports window, select the ports.
- Right-click, and select Configure I/O Ports.
- In the Configure Ports dialog box (see the following figure), edit the
following options, and click OK.Note: The Configure Ports dialog box options vary depending on the targeted device.
In the Configure Ports dialog box, the Fixed option is read only. To fix ports, select the ports in the I/O Ports window, right-click, and select Fix Ports, or enter the following Tcl command in the Tcl Console:
- I/O Standard
- Select the I/O standard constraint. The tool does not check the I/O standard when it is assigned. You can assign any I/O standard to any port, but this might result in errors when running DRCs.
- Drive Strength
- Select the drive strength value.
- Slew Type
- Select the slew type value.
- Pull Type
- Select the pull type value.
- Applies a weak logic High level on a 3-stateable output or bidirectional port to prevent it from floating when not being driven.
- Applies a weak logic Low level on a 3-stateable output or bidirectional port to prevent it from floating when not being driven.
- Applies a weak driver on an 3-stateable output or bidirectional port to preserve its value when not being driven.
- Does not apply a driver.Note: Alternatively, you can set the pull type constraint by clicking in the Pull Type column of the I/O Ports window.
- In Term Type
- (7 series devices only) Define the parallel termination properties of the input signal. For more information, see the 7 Series FPGAs SelectIO Resources User Guide (UG471)
- (UltraScale architecture-based devices only) Define the value of the on-die termination (ODT) at the input for both DCI and non-DCI versions of the standards supported. For more information, see the UltraScale Architecture SelectIO Resources User Guide (UG571)
- Indicates that the logical ports are user assigned. Ports must be fixed to ensure that the bitstream generates without errors.
set_property IS_LOC_FIXED true [get_selected_objects]Alternatively, you can enter the following Tcl command to fix ports:
set_property IS_LOC_FIXED true [get_ports <list_of_ports>]
CAUTION:For 7 series devices, Zynq-7000 UltraScale devices, UltraScale+ devices, and Zynq UltraScale+ MPSoCs, all I/O ports must have explicit values for the PACKAGE_PIN and IOSTANDARD constraints to generate a bitstream file. In the I/O Ports window, the word default is displayed in red to indicate that these values must be applied manually. You must apply extra care when assigning I/O standards, because these devices have Low and High voltage I/O banks.