The following figure shows the project design flow steps on the left. Horizontal arrows indicate the points in the project design flow when you can perform I/O and clock planning. The steps in the I/O and clock planning design flow are shown on the right.
The project design flow starts with an empty I/O planning project, an RTL design project, or a post-synthesis netlist project. Using any of these project types, you can perform the following steps in the I/O and clock planning design flow:
- Select Device and Compatible Parts
When selecting the part, determine the device size based on resource estimates for the final design. Select the package based on PCB requirements, such as critical routes to memories. Versal also has dedicated hard memory controller pins that cannot be used for other I/O operations. For designs using stacked silicon interconnect (SSI) technology, see this link in the UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949). In addition to the selected part, you can also identify alternate compatible parts, as described in Defining Alternate Compatible Parts.
Alternatively, you can select a supported targeted design platform board, which includes a Xilinx device and other components to provide a robust evaluation platform or rapid product development platform. For more information, see I/O and Clock Planning Using the Platform Board Flow.
- Select Configuration, DCI Cascade, and Internal VREF
A Xilinx device must be configured each time it is powered up. The bitstream is loaded into the device through special configuration pins that enable different configuration modes. For Versal, a device image is loaded. The configuration modes used in an application can affect the I/O planning of the design. It is important to determine and plan for the configuration modes before beginning I/O assignment. The configuration mode not only determines the connectivity of certain pins, it also determines the VCCO voltage required for the I/O bank that includes multi-function pins. For information, see Setting Device Configuration Modes.
Depending on the I/O standard, digitally controlled impedance (DCI) can control the output impedance of a driver or add a parallel termination to the driver, receiver, or both to match the characteristic impedance of a transmission line and improve signal integrity. DCI uses two multi-purpose reference pins in each I/O bank to control the impedance of the driver or the parallel-termination value for all of the I/Os in the bank.
Single-ended I/O standards with a differential input buffer require reference voltage (VREF). You can generate an internal VREF using the INTERNAL_VREF constraint, which eliminates the need to provide a particular reference voltage supply rail on the PCB. In 7 series and UltraScale™ architecture, this can free multi-purpose VREF pins in a given I/O bank for other I/O port assignments. For more information, see Setting Device Constraints.
- Configure I/O Ports and Clocks
The I/O ports on the device support multiple I/O-related constraints, such as IOSTANDARD, SLEW, and DRIVE. Configure these ports to support the standards required for the system-level design. The I/O standard definition might impact pin placement. For example, you can combine some I/O standards within a single I/O bank but not others. For more information, see Configuring I/O Ports.
Xilinx devices are subdivided into columns and rows of clock regions. A clock region contains configurable logic blocks (CLBs), I/O banks, digital signal processing (DSP) slices, block random access memory (RAM), interconnect, and associated clocking resources. Each I/O bank contains clock-capable input pins to bring system or board clocks onto the device and into clock routing resources. You must plan the use of these clock resources to distribute the clocks in your design across your device. Versal has specific clocking for high speed I/O that does not go out on global clocking. Be careful to ensure that you correctly clock these I/O. For more information, see Clock Planning.
Note: You cannot perform clock planning in an I/O planning project, because clock objects are not defined in this type of project.Recommended: Xilinx recommends that you use the Clocking wizard in the Vivado IP catalog to generate mixed-mode clock manager (MMCM) or phase-locked loop (PLL) modules to define clock connections. For information, see the Clocking Wizard LogiCORE IP Product Guide (PG065). You can also generate clocking with an I/O interface design through the Advanced I/O Wizard.
- Assign Memory Controller I/O Ports
The Memory IP defines a memory controller using a pre-engineered controller and physical layer (PHY) for interfacing FPGA designs to supported external memory devices. High-speed memory controllers as well as Ethernet IP and PCI Express® (PCIe) technology IP have specific pinout requirements driven by clocking and skew needs.
You must define the I/O physical pin assignments for the gigabit transceiver (GT), PCIe technology, and Memory IP as part of IP customization when the core is added to the design. Depending on the IP, to change the I/O assignments, you must re-customize the IP in the design. For information on working with and customizing IP, see the Vivado Design Suite User Guide: Designing with IP (UG896). For UltraScale architecture Memory IP, the I/O assignment is integrated into the standard I/O planning flow and does not require Memory IP customization. For more information, see I/O Planning for UltraScale Architecture Memory IP.Note: I/O planning projects do not read the physical pin assignments from the IP files for complex IP like the Memory Controllers, PCIe, or gigabit transceivers. See I/O and Clock Planning for IP with I/O Ports for more information.
- Place I/O Ports
You can interactively assign I/O ports in the design to package pins on the device using different methods. You can select individual I/O ports or groups of I/O ports called interfaces in the I/O Ports window and assign them to package pins in the Package window or to I/O pads in the Device window. The Advanced I/O Planner is also a tool for nibble and bank level pin placement. This tool allows for automatic placement that can understand all the I/O interfaces in an XPIO bank and place them effectively all at once. For information, see Placing I/O Ports.
You can also let the Vivado Design Suite automatically place I/O ports using information derived from the synthesized design. For information, see Automatically Placing I/O Ports.
- Run DRCs and SSN Analysis
After making I/O and clock assignments, it is critical that you analyze your design by running design rule checks (DRCs) and simultaneous switching noise (SSN) analysis. DRCs validate the current design against a specified set of design rules and report any violations. For information, see Running DRCs.
SSN analysis estimates the disruption that simultaneously switching outputs can cause on other output ports in an I/O bank. The calculation and estimates incorporate I/O bank-specific electrical characteristics into the prediction to identify potential noise-related issues in your design. For information, see Working with SSN Analysis.
Note: SSN analysis estimates are intended to identify potential noise-related issues in your design and are not intended as final design sign-off criteria.Recommended: Xilinx recommends that you run DRCs and SSN analysis after synthesis, prior to implementation, as well as after implementation. This enables you to catch issues early in the design cycle.
- Implement Design
You must implement the design before generating a bitstream to configure your Xilinx device. During implementation, the Vivado tools place design elements onto device resources, route the design network, and optimize to reduce power and close timing. For more information, see the Vivado Design Suite User Guide: Synthesis (UG901) and Vivado Design Suite User Guide: Implementation (UG904).
- Generate PCB Data (XDC, CSV, IBIS)
I/O and clock planning is an iterative process that includes the exchange of information between the PCB or system designer and the FPGA designer. It can begin with input from the PCB using a target device pinout imported from a CSV file. When you complete the steps in the I/O and clock planning flow, you can return the pinout, along with device models for signal integrity analysis, using a comma-separated values (CSV) file and I/O buffer information specification (IBIS) models. For more information, see Interfacing with the System Designer.