I/O and Clock Planning for SSI Technology Devices‌ - 2020.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2021-03-09
Version
2020.2 English

I/O and clock planning are critical when working with stacked silicon interconnect (SSI) technology. Because SSI technology devices have a larger die size, poor placement can create longer routes that increase power consumption and reduce performance. For information on pinout selection and clocking, see this link in the UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949).