The I/O Planning view layout includes the I/O Ports and Package Pins windows. If UltraScale architecture Memory IP exists in the design, the banners of both windows contain a message and a button to launch the Memory Bank/Byte Planner.
Figure 1. Invoking the Memory Bank/Byte Planner
Note: Alternatively, you can open the Memory Bank/Byte Planner by selecting .
You can use the Memory Bank/Byte Planner to either automatically or manually assign memory interface signal groups to specific byte groups within the I/O banks.
Figure 2. Memory Bank/Byte Planner
Note: If you use example designs generated directly from the Memory IP, the XDC file in the example design provides default I/O assignments that appear in the Memory Bank/Byte Planner.
The Memory Bank/Byte Planner includes the following features:
- Collapsible device resource tree
- Device resources, such as super logic regions (SLRs), I/O columns and banks, and
byte groups, appear in a collapsible and expandable tree that varies depending
on the selected device. You can collapse the tree to target a specific area of
the device, as shown in the following figure. The tree shows the resources in
the order they appear on the device, because memory interfaces must be assigned
to adjacent I/O banks.Figure 3. Collapsing the Device Resource Tree
- Cross-selection with other views
- When you select I/O banks and byte groups, the groups are also highlighted in
the Package and Device windows to aid in identifying the resources, as shown in
the following figure.Figure 4. Cross-Selecting Banks and Byte Groups
- DRC information
- At the top of the Memory Bank/Byte Planner (following figure), a DRC status
message provides information about DRC violations with a link to more
information.When you select I/O banks and byte groups, the groups are also
highlighted in the Package and Device windows to aid in identifying the
resources, as shown in the following figure.Figure 5. Showing DRC Violations
- Signal group information
- Click the Show Signal Group button to show
the list of signal groups for each Memory IP in the Signal Groups dialog
box.Figure 6. Showing Signal Groups