IES Simulator Compilation Options - 2020.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2020-11-23
Version
2020.2 English
Table 1. IES Compilation Options
Option Description
Verilog options Browse to set Verilog include path and to define macro
Generics/Parameters options Specify or browse to set the generic/parameter value
ies.compile.tcl.pre TCL file containing set of commands that should be invoked before launch of compilation
ies.compile.v93 Enable VHDL-93 features
ies.compile.relax Enable relaxed VHDL interpretation
ies.compile.load_glbl Load GLBL module
ies.compile.ncvhdlmore_options More NCVHDL compilation options
ies.compile.ncvlog.more_options More NCVLOG compilation options