Skipping Compilation - 2020.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2020-11-23
Version
2020.2 English

You can run simulation on an existing snapshot and skip the compilation (or recompilation) of the design by setting the SKIP_COMPILATION property on the simulation fileset:

set_property SKIP_COMPILATION 1 [get_filesets sim_1]
Note: Any change to design files after the last compilation is not reflected in simulation when you set this property.